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lt3689/lt3689-5 1 3689fa typical application features applications description 700ma step-down regulator with power-on reset and watchdog timer the lt ? 3689 is an adjustable frequency (350khz to 2.2mhz) monolithic step-down switching regulator with a power-on reset and watchdog timer. the regulator operates from inputs up to 36v and withstands transients up to 60v. low ripple burst mode ? operation maintains high ef? ciency at low output current while keeping output ripple below 15mv in a typical application, with input quiescent current of just 85a. shutdown circuitry reduces input supply current to less than 1a while en/uvlo is pulled low. using a resis- tor divider on the en/uvlo pin provides a programmable undervoltage lockout. current limit, frequency foldback and thermal shutdown provide fault protection. the reset and watchdog timeout periods are indepen- dently adjustable using external capacitors. tight accuracy speci? cations and glitch immunity ensure reliable reset operation of a system without false triggering. the open collector rst will pull down if output voltage drops 10% below the programmed value. the watchdog timer is pin-selectable for window or timeout modes. in timeout mode, wdo pulls low if too long of a period passes before a watchdog transition is detected. in window mode, the lt3689 monitors for wdi falling edges grouped too close together or too far apart. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 3.3v regulator with power-on reset timer and watchdog timer n wide input range: operation from 3.6v to 36v overvoltage lockout protects circuits through 60v transients n 85a i q at 12v in to 3.3v out n low ripple burst mode ? operation allows output ripple <15mv p-p n programmable, defeatable watchdog timer with window or timeout control n programmable power-on reset timer (por) n synchronizable, adjustable 350khz to 2.2mhz switching frequency n 700ma output switching regulator with internal power switch n fixed 5v or adjustable output voltage n 800mv feedback voltage n programmable input undervoltage lockout with hysteresis n 16-pin 3mm 3mm qfn and 16-pin msop packages n automotive electronic control units n industrial power supplies sw i/o i/o reset da fb rt sync f sw = 700khz wdi rst wdo v in p en/uvlo v in 4.5v to 36v transient to 60v 3.3v 700ma 100k c wdt 10nf t wdu = 182ms t wdl = 5.9ms 12h 10pf 22f 0.1f 316k gnd 20.5k lt3689 3689 ta01 bst out c por c wdt 2.2f c por 68nf t rst = 157ms ef? ciency load current (a) efficiency (%) power loss (mw) 0.0001 0.01 0.1 1 0.001 3689 ta01b v in = 12v v out = 3.3v f = 700khz l = 12h t a = 25c 40 50 60 70 80 30 20 10 0 90 100 10 1 1000
lt3689/lt3689-5 2 3689fa absolute maximum ratings v in , en/uvlo voltage (note 2) .................................60v bst voltage ..............................................................60v bst above sw voltage .............................................30v out, wde voltage .....................................................30v fb, rt, sync, w /t, wdi, rst , wdo voltage ...............6v c wdt , c por voltage .....................................................3v (note 1) order information lead free finish tape and reel part marking* package description temperature range lt3689emse#pbf lt3689emse#trpbf 3689 16-lead plastic msop with exposed pad C40c to 125c lt3689imse#pbf lt3689imse#trpbf 3689 16-lead plastic msop with exposed pad C40c to 125c lt3689hmse#pbf lt3689hmse#trpbf 3689 16-lead plastic msop with exposed pad C40c to 150c lt3689emse-5#pbf lt3689emse-5#trpbf 36895 16-lead plastic msop with exposed pad C40c to 125c lt3689imse-5#pbf lt3689imse-5#trpbf 36895 16-lead plastic msop with exposed pad C40c to 125c lt3689hmse-5#pbf lt3689hmse-5#trpbf 36895 16-lead plastic msop with exposed pad C40c to 150c lt3689eud#pbf lt3689eud#trpbf ldnd 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3689iud#pbf lt3689iud#trpbf ldnd 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3689eud-5#pbf lt3689eud-5#trpbf lffm 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3689iud-5#pbf lt3689iud-5#trpbf lffm 16-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ 1 2 3 4 5 6 7 8 wdo c wdt c por rt sync out bst v in 16 15 14 13 12 11 10 9 rst wdi w /t wde fb en/uvlo da sw top view 17 mse package 16-lead plastic msop ja = 43c/w, jc = 4.3c/w exposed pad (pin 17) is gnd, must be soldered to pcb 16 15 14 13 5 6 17 7 8 top view ud package 16-lead (3mm s 3mm) plastic qfn 9 10 11 12 4 3 2 1 bst v in sw da c wdt wdo rst wdi out sync rt c por en/uvlo fb wde w /t ja = 68c/w, jc = 4.2c/w exposed pad (pin 17) is gnd, must be soldered to pcb pin configuration operating junction temperature range (note 3) lt3689e ............................................. C40c to 125c lt3689i .............................................. C40c to 125c lt3689h ............................................ C40c to 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) msop ............................................................... 300c
lt3689/lt3689-5 3 3689fa electrical characteristics symbol parameter conditions min typ max units v in fixed undervoltage lockout l 3.4 3.7 v v in overvoltage lockout l 36 38 40 v quiescent current from v in v en/uvlo = 0.3v v out = 3v, not switching v out = 0v, not switching l 0.01 50 125 0.5 95 175 a a a quiescent current from out v en/uvlo = 0.3v v out = 3v, not switching (note 7) v out = 0v, not switching l 0.01 75 C5 0.5 150 C20 a a a lt3689-5 quiescent current from v in v en/uvlo = 0.3v v out = 5.5v (note 8) v out = 0v l 0.01 50 125 0.5 95 175 a a a lt3689-5 quiescent current from out v en/uvlo = 0.3v v out = 5.5v l 8 95 16 150 a a lt3689 fb voltage l 0.790 0.780 0.800 0.812 0.812 v v lt3689-5 output voltage l 4.950 4.900 5.000 5.050 5.100 v v lt3689 fb pin bias current v fb = 0.800v l C30 C100 na lt3689 fb voltage line regulation 5v < v in < 36v 0.005 %/v lt3689-5 output voltage line regulation 5.5v < v in < 36v 0.005 %/v f sw switching frequency r t = 4.02k r t = 31.62k l l 1.84 420 2 500 2.16 540 mhz khz t sw(off) switch off-time v bst = 12v 120 160 ns foldback frequency r t = 4.22k, v out = 0v 250 khz switch current limit (note 4) l 1.15 1.55 1.95 a switch v cesat i sw = 0.8a 450 mv switch leakage current 0.01 1 a da current limit 0.85 1.2 1.5 a boost schottky reverse leakage v bst = 12v, v out = 0v 0.1 5 a minimum bst above sw voltage 1.8 2.5 v bst pin current i sw = 0.8a 15 25 ma en/uvlo threshold voltage 1.150 1.260 1.350 v en/uvlo pin current v en/uvlo = 1.35v v en/uvlo = 1.15v 2.5 0. 01 4.1 1 5.5 a a en/uvlo pin current hysteresis i(v en/uvlo = 1.35v) C i(v en/uvlo = 1.15v) 2.8 3.8 4.8 a sync threshold voltage 0.4 0.8 1 v v rst reset threshold as % of v fb l 88 90 92 % t rst reset timeout period c por = 8200pf l 17 19 21 ms t wdu watchdog upper boundary c wdt = 1000pf l 17 19 21 ms t wdl watchdog lower boundary c wdt = 1000pf l 610 675 785 s v ol rst , wdo output voltage low i sink = 2.5ma, v out = 0v i sink = 100a, v out = 0v l l 0.15 0.05 0.4 0.3 v v v oh rst , wdo output voltage high (note 6) l v out C1 v the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, v out = 5v, unless otherwise noted. (note 3)
lt3689/lt3689-5 4 3689fa symbol parameter conditions min typ max units t uv uv detect to rst asserted step v fb from 0.9v to 0.5v l 10 30 65 s wdi input threshold l 0.4 0.95 1.15 v wdi input pull-up current C2 a wdi input pulse width l 300 ns w /t threshold voltage l 0.4 0.8 1 v w /t input pull-down current 2.6 a wde threshold voltage l 0.4 0.8 1 v wdo pull-up current (note 6) C0.6 C0.85 a rst pull-up current (note 6) C0.6 C0.85 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: absolute maximum voltage at v in and en/uvlo pins is 60v for nonrepetitive 1 second transients, and 36v for continuous operation. note 3: the lt3689e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3689i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3689h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 4 : current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 6: the output of rst and wdo has a weak pull-up to v out of typically 1a. however, external pull-up resistors may be used when faster rise times are required or for v oh higher than v out . note 7: polarity speci? cation for all currents into pins is positive. all voltages are referenced to gnd unless otherwise speci? ed. note 8: for the lt3689-5, v out is set to 5.5v to ensure the switching. electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, v out = 5v, unless otherwise noted. (note 3) typical performance characteristics ef? ciency, v out = 5v ef? ciency, v out = 3.3v ef? ciency, v out = 1.8v load current (a) 0 efficiency (%) 0.4 0.2 0.6 0.3 0.1 0.5 0.7 3689 g01 t a = 25c f = 1mhz v in = 12v v in = 24v v in = 32v 85 90 80 75 70 65 95 0 0.4 0.2 0.6 0.3 0.1 0.5 0.7 load current (a) efficiency (%) 85 80 75 70 65 90 3689 g02 t a = 25c f = 700khz v in = 12v v in = 24v v in = 32v load current (a) efficiency (%) 70 75 65 60 55 50 80 3689 g03 t a = 25c f = 1mhz v in = 5v v in = 12v 0 0.4 0.2 0.6 0.3 0.1 0.5 0.7
lt3689/lt3689-5 5 3689fa typical performance characteristics no-load supply current vs v in no-load supply current maximum load current, 5v out maximum output current, 3.3v out switch current limit vs duty cycle switch current limit vs temperature switch voltage drop maximum v in for full frequency maximum v in for full frequency input voltage (v) 0 supply current (a) 80 100 120 35 60 40 10 20 5 15 25 30 40 20 0 140 3689 g04 t a = 25c temperature (c) C50 0 supply current (a) 200 400 600 C25 0 25 50 100 75 125 800 100 300 500 700 150 3689 g05 catch diode: diodes inc. b140hb v in = 12v v out = 3.3v increased supply current due to catch diode leakage at high temperature 0 0.4 0.8 1.2 0.2 0.6 1.0 1.4 v in (v) 6 load current (a) 12 18 30 24 36 3689 g06 minimum typical t a = 25c l = 12h f = 1mhz 0 0.4 0.2 0.6 0.3 0.1 0.5 0.7 load current (a) 0 v in (v) 10 20 30 40 5 15 25 35 3689 g07 v o = 5v l = 6.8h f = 2mhz sync = 5v t a = 25c t a = 85c 0 0.4 0.2 0.6 0.3 0.1 0.5 0.7 load current (a) 0 v in (v) 10 20 30 5 15 25 35 3689 g08 v o = 3.3v l = 4.7h f = 2mhz sync = 3.3v t a = 25c t a = 85c v in (v) 4 0 load current (a) 0.4 0.8 1.2 8 12 16 20 28 24 32 0.2 0.6 1.0 36 3689 g09 t a = 25c l = 12h f = 700khz minimum typical duty cycle (%) 0 0 current limit (a) 0.4 0.8 1.2 1.6 2.0 20 40 60 80 100 3689 g10 t a = 25c sync = low minimum typical temperature (c) 0 current limit (a) 0.5 1.0 1.5 2.0 3689 g11 sync = high sync = low C50 C25 0 25 50 100 75 125 150 switch current (ma) 0 voltage drop (mv) 400 500 300 200 400 800 200 600 1000 100 0 600 3689 g12 t a = 125c t a = 25c t a = C50c
lt3689/lt3689-5 6 3689fa typical performance characteristics switching frequency vs r t switching frequency frequency foldback minimum switch on-time overvoltage lockout v in fixed undervoltage lockout bst pin current feedback voltage switch current (ma) 0 bst pin current (ma) 15 20 10 5 400 800 200 600 1000 0 25 3689 g13 t a = 125c t a = C50c t a = 25c temperature (c) 0.790 feedback voltage (v) 0.795 0.800 0.805 0.810 3689 g14 C50 C25 0 25 50 100 75 125 150 frequency (mhz) 0 0 r t (k) 10 20 30 40 50 0.4 0.8 1.2 1.6 3689 g16 2 2.4 t a = 25c temperature (c) 500 frequency (khz) 600 700 800 900 550 650 750 850 3689 g17 ?50 25 75 ?25 0 50 100 150 125 r t = 20.5k fb voltage (mv) 0 switching frequency (khz) 800 1000 600 400 200 300 500 100 400 600 800 700 900 200 0 1200 3689 g18 t a = 25c r t = 12.7k temperature (c) 0 minimum on-time (ns) 20 60 100 140 40 80 120 3689 g19 ?50 25 75 ?25 0 50 100 150 125 i load = 700ma temperature (c) 36 overvoltage lockout (v) 37 38 39 40 3689 g20 C50 C25 0 25 50 100 75 125 150 temperature (c) 3.1 v in uvlo (v) 3.2 3.3 3.4 3.5 3.6 3689 g21 v in falling v in rising C50 C25 0 25 50 100 75 125 150 output voltage temperature (c) output voltage (v) 3689 g15 C50 C25 0 25 50 100 75 125 150 4.95 4.97 4.99 5.01 5.03 5.05 4.96 4.98 5.00 5.02 5.04
lt3689/lt3689-5 7 3689fa typical performance characteristics en/uvlo pin current en/uvlo pin threshold boost diode forward voltage en/uvlo hysteresis current switching waveform: burst mode operation switching waveform: transition from burst mode to full frequency switching waveform: full frequency continuous operation power-on-reset threshold vs temperature v en/uvlo (v) en/uvlo pin current (a) 3689 g22 05 10 15 20 30 25 35 6 7 5 4 1 0 3 2 t a = 150c t a = C50c t a = 25c temperature (c) C50 1.200 en/uvlo threshold (v) 1.220 1.240 1.260 C25 0 25 50 100 75 125 1.280 1.300 1.210 1.230 1.250 1.270 1.290 150 3689 g23 en/uvlo threshold rising en/uvlo threshold falling v in = 12v boost diode current (ma) boost diode voltage (mv) 3689 g24 010 20 30 40 50 600 700 800 500 400 100 0 300 900 200 t a = 150c t a = 25c t a = C50c temperature (c) 3.0 en/uvlo hysteresis current (a) 3.5 4.0 4.5 5.0 3689 g25 C50 C25 0 25 50 100 75 125 150 5s/div v out 10mv/div v in = 12v, front page application i load = 6ma v sw 5v/div i l 0.2a/div 3689 g26 1s/div v out 10mv/div v in = 12v, front page application i load = 60ma v sw 5v/div i l 0.2a/div 3689 g27 1s/div v out 10mv/div v in = 12v, front page application i load = 600ma v sw 10v/div i l 0.5a/div 3689 g28 temperature (c) 0.710 por threshold (v) 0.715 0.720 0.725 0.730 3689 g29 C50 C25 0 25 50 100 75 125 150
lt3689/lt3689-5 8 3689fa typical performance characteristics watchdog upper boundary period watchdog lower boundary period reset timeout period watchdog upper boundary period vs capacitance reset timeout period vs capacitance transient duration vs por comparator overdrive por comparator overdrive voltage as percentage of reset threshold, v rst (%) 0.10 400 transient duration (s) 500 600 700 800 1.00 10.00 100.00 300 200 100 0 3689 g30 reset occurs above the curve temperature (c) 17 upper boundary period, t wdu (ms) 18 19 20 21 3689 g31 C50 C25 0 25 50 100 75 125 150 c wdt = 1nf murata: grm1882c1h102fa01 temperature (c) 5.0 lower boundary period, t wdl (ms) 5.5 6.0 6.5 7.0 3689 g32 C50 C25 0 25 50 100 75 125 150 c wdt = 10nf murata: grm1885c1h102fa01 temperature (c) 17 reset timeout period, t rst (ms) 18 19 20 21 3689 g33 C50 C25 0 25 50 100 75 125 150 c por = 8.2nf murata: grm2195c1h822fa01 0.001 0.01 0.1 1 10 100 1000 c wdt pin capicitance, c wdt (nf) upper boundary period, t wdu (ms) 3689 g34 100 10000 0.1 1 100000 1000 10 c por pin capicitance, c por (nf) reset timeout period, t rst (ms) 3689 g35 10 1000 0.01 0.1 10000 100 1 0.001 0.01 0.1 1 10 100 1000 10000 watchdog lower boundary period vs capacitance c wdt pin capicitance, c wdt (nf) lower boundary period, t wdl (ms) 3689 g36 10 1000 0.01 0.1 10000 100 1 0.001 0.01 0.1 1 10 100 1000 10000
lt3689/lt3689-5 9 3689fa pin functions bst: the bst pin is used to provide drive voltage higher than the input voltage to the internal npn power switch. v in : the v in pin supplies current to the lt3689s internal circuitry and to the internal power switch and must be locally bypassed. sw: the sw pin is the output of the internal power switch. connect this pin to the inductor, catch diode and boost capacitor. da : tie the da pin to the anode of the external catch schottky diode. if the da pin current exceeds 1.2a, which could occur in an overload or short-circuit condi- tion, switching is disabled until the da pin current falls below 1.2a. en/uvlo: the en/uvlo pin is used to put the lt3689 in shutdown mode. pull the pin below 0.3v to shut down the lt3689. the 1.26v threshold can function as an accurate undervoltage lockout (uvlo), preventing the regulator from operating until the input voltage has reached the programmed level. fb : the lt3689 regulates the feedback pin to 0.800v. con- nect the feedback resistor divider tap to this pin. for the ? xed lt3689-5 output, this pin can be used to connect a phase lead capacitor between the out pin and fb pin to optimize transient response. wde : watchdog timer enable pin. this pin disables the watchdog timer if the wde voltage exceeds 1v. wdo is high in this condition. w /t: setting w /t low puts the lt3689 watchdog timer into window mode. if two or more negative edges occur on wdi before the watchdog lower boundary (t wdl ) period expires, or no negative edge occurs within the watchdog upper boundary (t wdu ) period, the part will set wdo low. if w /t is set high, the part will only set wdo low if no transition occurs within the watchdog upper boundary period. wdi: watchdog timer input pin. this pin receives the watchdog signal from a microprocessor. if the appropriate signal is not received, the part will pulse wdo low for a period equal to the reset timeout period. the watchdog timer is disabled until the wdo pin goes high again. rst : active low, open collector logic output with a weak pull-up to v out . after v out rises above 90% of its pro- grammed value, the reset remains asserted for the period set by the capacitor on the c por pin. wdo : active low, open collector logic output with weak pull-up to v out . wdo pulls low if the wde is enabled and the microprocessor fails to drive the wdi pin of the lt3689 with an appropriate signal. c wdt : watchdog timer programming pin. place a capa- citor (c wdt ) between this pin and ground to adjust the watchdog upper and lower boundary period. to determine the watchdog upper boundary period, and the lower bound- ary period, use the following equations: t wdu = 18.2 ? c wdt (watchdog upper boundary period) t wdl = 0.588 ? c wdt (watchdog lower boundary period) t wdu and t wdl are in ms and c wdt is in nf. as an example, a 47nf capacitor will generate an 855ms watchdog upper boundary period and a 27.6ms watchdog lower boundary period. c por : reset delay timer programming pin. attach an external capacitor (c por ) to gnd to set a reset delay time of 2.3ms/nf. rt: sets the internal oscillator frequency. tie a 31.6k resis- tor from rt to gnd for a 500khz switching frequency. sync: drive the sync pin with a logic level signal with positive and negative pulse widths of at least 80ns. the r t resistor should be chosen to set the lt3689 switching frequency at least 20% below the lowest synchronization input frequency. out: the out pin supplies current to the internal circuitry when out is above 3v, reducing input quiescent current. the internal schottky diode is connected from out to bst, providing the charging path for the boost capacitor. for the lt3689-5, this pin connects to the internal feedback divider that programs the ? xed 5v output. gnd: ground. tie the exposed pad directly to the ground plane. the exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the device must be soldered to the circuit board for proper operation.
lt3689/lt3689-5 10 3689fa block diagram + C + C oscillator transition detect watchdog timer adjustable reset pulse generator burst mode operation detect v c clamp soft-start internal 0.8v ref slope comp r v in v in v out en/uvlo rt bst sw switch latch gnd v out c3 l1 d1 disable out sync error amp out r t c1 fb fb 80mv v in 3.4v r sen 2a 2a 22a 22a 1a 1a s q 3 da c2 r1 r2 out 525k lt3689-5 only 100k ? + ? + c wdt wdi r c v c c c out rst c por + wde wdo w /t 3689 bd
lt3689/lt3689-5 11 3689fa timing diagrams 3689 td t rst t wdu t wdu t < t wdl t rst t rst t rst t uv v out power-on reset timing watchdog timing ( w /t = high), timeout mode v uv wdo wdi wdi wdo rst watchdog timing ( w / t = low), window mode t uv = time required to assert rst low once v out goes below v uv t rst = programmed reset period t wdu = watchdog upper boundary period t wdl = watchdog window mode lower boundary period v uv = output voltage reset threshold
lt3689/lt3689-5 12 3689fa operation the lt3689 is a constant-frequency, current mode step- down regulator with a watchdog and a reset timer that allows microprocessor supervisory functions. operation can be best understood by referring to the block diagram. keeping the en/uvlo pin at ground completely shuts off the part drawing minimal current from the v in source. to turn on the internal bandgap and the rest of the logic cir- cuitry, raise the en/uvlo pin above the accurate threshold of 1.26v. also, v in needs to be higher than 3.7v for the part to start switching. switching regulator operation an oscillator, with frequency set by r t , enables an rs ? ip- ? op, turning on the internal power switch. an ampli? er and comparator monitor the current ? owing between the v in and sw pins, turning the switch off when this current reaches a level determined by the voltage at v c . an error ampli? er measures the output voltage through the resistor divider tied to the fb pin and servos the v c voltage. if the error ampli? ers output increases, more current is delivered to the output; if it decreases, less current is delivered. an active clamp on the v c voltage provides current limit. an internal regulator provides power to the control circuitry. the bias regulator normally draws current from the v in pin, but if the out pin is connected to an external volt- age higher than 3v, bias current will be drawn from the external source (typically the regulated output voltage). this improves ef? ciency. the out pin also provides a current path to the internal boost diode that charges up the boost capacitor. the switch driver operates either from the v in or from the bst pin. an external capacitor is used to generate a voltage at the bst pin that is higher than the v in supply. this allows the driver to fully saturate the internal bipolar npn power switch for ef? cient operation. to further optimize ef? ciency, the lt3689 automatically switches to burst mode operation in light load situations. between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input sup- ply current to 85a in a typical application. the oscillator reduces the lt3689s operating frequency when the volt- age at the fb pin is low. this frequency foldback helps to control the output current during start-up and overload conditions. a comparator monitors the current ? owing through the catch diode via the da pin. this comparator delays switch- ing if the diode current goes higher than 1.2a (typical) during a fault condition such as a shorted output with high input voltage. the switching will only resume once the diode current has fallen below the 1.2a limit. this way the da comparator regulates the valley current of the inductor to 1.2a during a short-circuit. the lt3689 has an overvoltage protection feature which disables switching when the v in goes above 38v (typical) during transients. when switching is disabled, the lt3689 can safely sustain transient input voltages up to 60v. power-on reset and watchdog timer operation the lt3689 has a power-on reset (por) comparator that monitors the regulated output voltage. if the output volt- age is below 10% of the regulation value, the rst pin is pulled low. once the output voltage crosses over 90% of the regulation value, a reset timer is started and rst is released after the programmed reset delay time. the reset delay is programmable through the c por pin. the watchdog typically monitors a microprocessors activ- ity. the watchdog can be enabled or disabled by applying a logic signal to the wde pin. the watchdog can be oper- ated in either timeout or window mode by applying a logic signal to the w /t pin. in timeout mode, the microprocessor is required to change the logic state of the wdi pin on a periodic basis in order to clear the watchdog timer and to prevent the wdo from going low. in window mode, the watchdog timer requires successive negative edges on the wdi pin to come within a programmed time window to keep wdo from going low. therefore, in window mode, if the time between the two negative wdi edges is too short or too long, then the wdo pin will be pulled low. when the wdo pin goes low, either in timeout or in window mode, the reset timer turns on and keeps the wdo pin low. the wdo pin will go high again once the reset timer expires or the rst pin goes low when the output voltage falls 10% below the regulation value. both the timeout and window periods can be set through the c wdt pin.
lt3689/lt3689-5 13 3689fa the output voltage is programmed with a resistor divider between the output and the fb pin. choose 1% resistors according to: r1 = r2 v out 0.8v 1 for reference designators, refer to the block diagram. setting the switching frequency the lt3689 uses a constant-frequency pwm architecture that can be programmed to switch from 350khz to 2.2mhz by using a resistor tied from the rt pin to ground. table 1 shows the r t values for various switching frequencies. table 1. switching frequency vs r t switching frequency (mhz) r t (k) 0.35 48.7 0.5 31.6 0.6 24.9 0.7 20.5 0.8 16.9 0.9 14.7 1 12.7 1.2 9.53 1.4 7.5 1.6 6.04 1.8 4.87 2 4.02 2.2 3.16 applications information operating frequency tradeoffs selection of the operating frequency is a tradeoff between ef? ciency, component size and maximum input voltage. the advantage of high frequency operation is that smaller inductor and capacitor values may be used. the disad- vantages are lower ef? ciency, and narrower input voltage range at constant-frequency. the highest constant-switch- ing frequency (f sw(max) ) for a given application can be calculated as follows: f vv tvvv sw max out d on min in sw d () () ? = + + () where v in is the typical input voltage, v out is the output voltage, v d is the catch diode drop (~0.5v) and v sw is the internal switch drop (~0.5v at maximum load). if the lt3689 is programmed to operate at a frequency higher than f sw(max) for a given v in input voltage, the lt3689 enters pulse-skipping mode, where it skips switching cycles to maintain regulation. at frequencies higher than f sw(max) , the lt3689 no longer operates with constant- frequency. the lt3689 enters pulse-skipping mode at frequencies higher than f sw(max) because of the limita- tion on the lt3689s minimum on-time of 130ns. as the switching frequency is increased above f sw(max) , the part is required to switch for shorter periods of time to maintain the same duty cycle. delays associated with turning off the power switch dictate the minimum on-time of the part. when the required on-time decreases below the minimum on-time of 130ns, the switch pulse width remains ? xed at 130ns (instead of becoming narrower to accommodate the duty cycle requirement). the inductor current ramps up to a value exceeding the load current and the output ripple increases. the part then remains off until the output voltage dips below the programmed value before it begins switching again.
lt3689/lt3689-5 14 3689fa maximum operating voltage the maximum input voltage for lt3689 applications depends on switching frequency, the absolute maximum ratings of the v in and bst pins, and by the minimum duty cycle (dc min ). the lt3689 can operate from input voltages up to 36v, and safely withstand input transient voltages up to 60v. note that while v in > 38v (typical), the lt3689 will stop switching, allowing the output to fall out of regulation. dc min = t on(min) ? f sw where t on(min) is equal to 130ns (for t j > 125c t on(min) is equal to 150ns) and f sw is the switching frequency. running at a lower switching frequency allows a lower minimum duty cycle. the maximum input voltage before pulse-skipping occurs depends on the output voltage and the minimum duty cycle: v vv dc vv in ps out d min dsw () ? = + + example: f sw = 790khz, v out = 3.3v, dc min = 130ns ? 790khz = 0.103 v vv vvv in ps () .. . ?. . = + += 33 04 0 103 04 04 36 the lt3689 will regulate the output current at input volt- ages greater than v in(ps) . for example, an application with an output voltage of 1.8v and switching frequency of 1.5mhz has a v in(ps) of 11.3v, as shown in figure 1. figure 2 shows operation at 24v. output ripple and peak inductor current have signi? cantly increased. a saturating inductor may further reduce performance. for input volt- ages over 30v, there are restrictions on the inductor size and saturation rating. see the inductor selection section for more details. in pulse-skipping mode, the lt3689 skips switching pulses to maintain output regulation. above 38v (typical) switching will stop. transients of up to 60v are acceptable, regardless of switching frequency. minimum operating voltage range the minimum input voltage is determined either by the lt3689s minimum operating voltage of ~3.4v or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc vv vv v out d in sw d = + + ? unlike many ? xed frequency regulators, the lt3689 can extend its duty cycle by remaining on for multiple cycles. the lt3689 will not switch off at the end of each clock cycle if there is suf? cient voltage across the boost capacitor (c3 in the block diagram). eventually, the voltage on the boost capacitor falls and requires refreshing. circuitry detects applications information figure 1. operation below v in(ps) . v in = 10v, v out = 1.8v and f sw = 1.5mhz figure 2. operation above v in(ps) . v in = 24v, v out = 1.8v and f sw = 1.5mhz. output ripple and peak inductor current increase 5s/div v out 50mv/div (ac) i l 0.5a/div 3689 f01 5s/div v out 50mv/div (ac) i l 0.5a/div 3689 f02
lt3689/lt3689-5 15 3689fa this condition and forces the switch to turn off, allowing the inductor current to charge up the boost capacitor. this places a limitation on the maximum duty cycle. the maximum duty cycle that the lt3689 can sustain is 90%. from this dc max number, the minimum operating voltage can be calculated using the following equation: v vv vv in min out d dsw () . = + ? + 090 example: v out = 3.3v v vv vvv in min () .. . ?. . . = + += 33 04 090 04 04 41 inductor selection and maximum output current a good ? rst choice for the inductor value is: lv v mhz f out f sw =+ ()? . 22 where v f is the voltage drop of the catch diode (~0.4v), f sw is the switching frequency in mhz, and l is in h. the inductors rms current rating must be greater than the maximum load current and its saturation current should be at least 30% higher. for robust operation in fault con- ditions (start-up or short-circuit) and high input voltage (>30v), use an 8.2h or greater inductor (for t j > 125c, use 10h or larger) with a saturation rating of 2.5a, or higher. to keep the ef? ciency high, the series resistance (dcr) should be less than 0.15 and the core mate- rial should be intended for high frequency applications. table 2 lists several vendors and suitable types. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to- peak inductor ripple current. the lt3689 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt3689 will deliver depends on the switch current limit, the inductor value, and the input and output volt- ages. also, if the inductor currents bottom peak exceeds the da current limit (i lim(da) ) at high output currents then the da current comparator will regulate the bottom peak to i lim(da) . this will result in higher inductor ripple current and will further limit the max output current. the da current limit consists of a dc and an ac component. the nominal dc component is ? xed at 1.2a. the ac component depends on the output voltage, inductor size and a ? xed time delay between the da comparator turn- ing off and switch turning on. therefore, the da current limit i lim(da) will increase as the output voltage collapses under overload conditions. i lim(da) = 1.2a ? v out + v d () l ? 0.25s table 2. inductor vendors vendor url part series inductance range (h) size (mm) sumida www.sumida.com cdrh4d28 cdrh5d28 1.2 to 4.7 2.5 to 10 4.5 4.5 5.5 5.5 toko www.toko.com a916cy d585lc 2 to 12 1.1 to 39 6.3 6.2 8.1 8 wrth elektronik www.we-online.com we-tpc(m) we-pd2(m) 1 to 10 2.2 to 22 4.8 4.8 5.2 5.8 applications information
lt3689/lt3689-5 16 3689fa choose an inductor using the previous inductor selection equation to guarantee 700ma of output current. if using a smaller inductor, check the da current limit equation to verify that the da circuitry will not lower the switching frequency. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: i l = (1 ? dc)(v out + v d ) l?f sw where f sw is the switching frequency of the lt3689 and l is the value of the inductor. the peak inductor and switch current is: i sw(pk) = i l(pk) = i out + i l 2 to maintain output regulation, this peak current must be less than the lt3689s switch current limit i lim . i lim is at least 1.5a for at low duty cycles and decreases linearly to 0.87a at dc = 85%. the maximum output current is a function of the chosen inductor value. i out(max) = i lim ? i l 2 = 1.15a ? (1 ? 0.2 8 ?dc) ? i l 2 choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. one approach to choosing the inductor is to start with the preceding simple rule, determine the available inductors, and choose one to meet cost or space goals. next, use these equations to check that the lt3689 will be able to deliver the required output current. note again that these equations assume that the inductor current is continu- ous. discontinuous operation occurs when i out is less than i l /2. of course, such a simple design guide will not always result in the optimum inductor for the application. a larger value inductor provides a slightly higher maximum load current and will reduce the output voltage ripple. if the load is lower than 0.7a, decrease the value of the inductor and operate with a higher ripple current. this allows the use of a physically smaller inductor, or one with a lower dcr resulting in higher ef? ciency. there are graphs in the typical performance characteristics section of this data sheet that show the maximum load current as a function of input voltage for several popular output volt- ages. low inductance may result in discontinuous mode operation, which is okay but further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technology application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations: l vv f min out d sw = + () 14 . where l min is in h, v out and v d are in volts, and f sw is in mhz. input capacitor bypass the input of the lt3689 circuit with a ceramic capacitor of an x7r or x5r type. y5v types have poor performance over temperature and applied voltage, and should not be used. the minimum value of input capaci- tance depends on the switching frequency. use an input capacitor of 1f or more for switching frequencies be- tween 1mhz to 2.2mhz, and 2.2f or more for frequen- cies lower than 1mhz. if the input power source has high impedance, or there is signi? cant inductance due to long wires or cables, additional bulk capacitance may be nec- essary. this can be provided with a lower performance electrolytic capacitor. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt3689 input and to force this very high frequency switching current into a tight local loop, minimizing emi. a ceramic capacitor is capable of this task, but only if it is placed close to the lt3689 and the catch diode (see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt3689. a ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. if the applications information
lt3689/lt3689-5 17 3689fa lt3689 circuit is plugged into a live supply, the input volt- age can ring to twice its nominal value, possibly exceeding the lt3689s voltage rating. for a complete discussion, see linear technologys application note 88. output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it ? lters the square wave generated by the lt3689 to produce the dc output. in this role it determines the output ripple, and low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the lt3689s control loop. ceramic capacitors have very low equivalent series resistance (esr) and provide the best ripple performance. a good starting value is: c vf out out sw = 50 where f sw is in mhz, and c out is the recommended out- put capacitance in f. use x5r or x7r types, which will provide low output ripple and good transient response. transient performance can be improved with a high value capacitor, but a phase lead capacitor across the feedback resistor r1 may be required to get the full bene? t (see the frequency compensation section). high performance electrolytic capacitors can be used for the output capacitor. low esr is important, so choose one that is intended for use in switching regulators. the esr should be speci? ed by the supplier and should be 0.1 or less. such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance because the capacitor must be large to achieve low esr. table 3 lists several capacitor vendors. table 3. capacitor vendors vendor phone url panasonic (714) 373-7366 www.panasonic.com kemet (864) 963-6300 www.kemet.com sanyo (408) 749-9714 www.sanyovideo.com murata (408) 436-1300 www.murata.com avx www.avxcorp.com taiyo yuden (864) 963-6300 www.taiyo-yuden.com catch diode the catch diode conducts current only during switch-off time. average forward current in normal operation can be calculated from: i ivv v d avg out in out in () () = ? where i out is the output load current. the only reason to consider a diode with a larger current rating than neces- sary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current limit. peak reverse voltage is equal to the regulator input voltage. use a schottky diode with a reverse voltage rating greater than the input voltage. the overvoltage protection feature in the lt3689 will keep the switch off when v in > 38v (typical), which allows the use of a 40v rated schottky even when v in ranges up to 60v. table 4 lists several schottky diodes and their manufacturers. applications information
lt3689/lt3689-5 18 3689fa table 4. diode vendors part number v r (v) i ave (a) v f at i ave (mv) on semiconductor mbrm120e mbrm140 20 40 1 1 530 550 diodes inc. b120 b130 b140 b0540w b140hb 20 30 40 40 40 1 1 1 0.5 1 500 500 500 510 530 ceramic capacitors ceramic capacitors are small, robust and have very low esr. however, ceramic capacitors can cause problems when used with the lt3689 due to their piezoelectric nature. when in burst mode operation, the lt3689s switching frequency depends on the load current, and at very light loads the lt3689 can excite the ceramic capaci- tor at audio frequencies, generating audible noise. since the lt3689 operates at a lower current limit during burst mode operation, the noise is typically very quiet. if this noise is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. frequency compensation the lt3689 uses current mode control to regulate the output, which simpli? es loop compensation. in particular, the lt3689 does not require the esr of the output capaci- tor for stability, allowing the use of ceramic capacitors to achieve low output ripple and small circuit size. figure 3 shows an equivalent circuit for the lt3689 control loop. the error amp is a transconductance ampli? er with ? nite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance ampli? er generating an output current proportional to the voltage at the v c node. note that the output capacitor, c1, integrates this current, and that the capacitor on the v c node (c c ) integrates the error ampli- ? er output current, resulting in two poles in the loop. r c provides a zero. with the recommended output capacitor, the loop crossover occurs above the r c c c zero. this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. with a larger ceramic capacitor (very low esr), crossover may be lower and a phase lead capacitor (c pl ) across the feedback divider may improve the phase margin and transient response. large electrolytic capacitors may have an esr large enough to create an additional zero, and the phase lead may not be necessary. applications information figure 3. model for the loop response C + C + 800mv v c lt3689 gnd 3689 f03 r1 out esr error amplifier current mode power stage fb r2 3m r c 37k c c 100pf c1 c1 g m = 300a/v g m = 1.2a/v + c pl 0.7v
lt3689/lt3689-5 19 3689fa most applications running at v in greater than 20v will require a small phase lead capacitor, ranging from 2pf to about 30pf, between the fb pin and v out for good transient response. the circuits in the typical applications section use the appropriate phase lead capacitors and are stable at all input voltages. if the output capacitor is different than the recommended capacitor, stability should be checked across all operating conditions, including load current, input voltage and tem- perature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. figure 4 shows the transient response when the load current is stepped from 360ma to 720ma and back to 360ma. low ripple burst mode operation and pulse-skipping mode the lt3689 is capable of operating in either low ripple burst mode operation or pulse-skipping mode, which is selected using the sync pin. see the synchronization section for details. to enhance ef? ciency at light loads, the lt3689 can be operated in low ripple burst mode operation that keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the lt3689 delivers single cycle bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. because the lt3689 delivers power to the output with single, low current pulses, the output ripple is kept below 15mv for a typical application. the lt3689-5 has a slightly higher output ripple of 25mv. this higher ripple can be reduced by using a larger output capacitor. in addition, v in and out quiescent currents are reduced to typically 50a and 75a, respectively, during the sleep time. as the load current decreases towards a no-load condition, the percentage of time that the lt3689 operates in sleep mode increases and the average input current is greatly reduced, resulting in high ef? ciency even at very low loads (see figure 5). at higher output loads (above approximately 60ma at v in = 12v for the front page application) the lt3689 will be running at the frequency programmed by the r t resistor, and will be operating in standard pwm mode. the transi- tion between pwm and low ripple burst mode operation is seamless, and will not disturb the output voltage. if low quiescent current is not required, the lt3689 can oper- ate in pulse-skipping mode. the bene? t of this mode is that the lt3689 will enter full frequency standard pwm operation at a lower output load current than when in burst mode operation. the front page application circuit will switch at full frequency at output loads higher than about 15ma at 12v in . applications information figure 4. transient load response of the lt3689 front page application as the load current is stepped from 360ma to 720ma. v out = 3.3v, v in = 12v figure 5. burst mode operation 10s/div v out 50mv/div i l 250ma/div 3689 f04 5s/div v out 10mv/div v in = 12v, front page application i load = 8ma v sw 5v/div i l 0.2a/div 3689 f05
lt3689/lt3689-5 20 3689fa bst and out pin considerations capacitor c3 and the internal boost schottky diode (see the block diagram) are used to generate a boost voltage that is higher than the input voltage. in most cases, a 0.1f capacitor will work well. figure 6 shows three ways to ar- range the boost circuit. the bst pin must be more than 2.3v above the sw pin for best ef? ciency. for outputs of 3v and above, the standard circuit (figure 6a) is best. for outputs between 2.8v and 3v, use a 0.47f boost capaci- tor. a 2.5v output presents a special case because it is marginally adequate to support the boosted drive stage while using the internal boost diode. for reliable bst pin operation with 2.5v outputs, use a good external schottky diode (such as on semiconductors mbr0540), and a 0.47f boost capacitor (see figure 6b). for lower output voltages, the boost diode can be tied to the input (figure 6c), or to another supply greater than 2.8v. the circuit in figure 6a is more ef? cient because the bst pin current and out pin quiescent current comes from a lower volt- age source. ensure that the maximum voltage ratings of the bst and out pins are not exceeded. the minimum operating voltage of an lt3689 application is limited by the minimum input voltage (3.7v) and by the maximum duty cycle, as outlined in the minimum operating voltage range section. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt3689 is turned on with its en/uvlo pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. for lower start-up voltage, the boost diode can be tied to v in ; however, this restricts the input range to one-half of the absolute maximum rating of the bst pin. applications information figure 6. three circuits for generating the boost voltage v in bst sw out v in v out 2.2f c3 gnd lt3689 v in bst sw out v in v out 2.2f c3 d2 gnd lt3689 v in bst sw out v in v out 2.2f c3 gnd lt3689 3689 f06 (6a) for v out > 2.8v (6b) for 2.5v < v out < 2.8v (6c) for v out < 2.5v; v in(max) = 30v
lt3689/lt3689-5 21 3689fa another way to lower the start-up voltage is by using a resistor divider on the en/uvlo pin (see the shutdown and undervoltage lockout section). a resistor divider on en/uvlo pin programs the turn-on threshold to slightly higher than the minimum v in voltage required to run at full load. below the en/uvlo high voltage, the part will stay shut off and the output cap will remain discharged during the worse case slow v in ramp. when the en/uvlo pin crosses the en/uvlo high threshold, the part will turn on and the empty output capacitor will provide enough load to bring the output voltage in regulation. this technique signi? cantly lowers the start-up voltage of the circuit. the plot in figure 7 depicts the minimum load required to start and run (as a function of input voltage). it also depicts the bene? t of programming the en/uvlo threshold to lower the start-up voltage at low load currents. at light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. this reduces the minimum input voltage to approximately 300mv above v out . at higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle of the lt3689, requiring a higher input voltage to maintain regulation. soft-start the lt3689 has an internal soft-start that gradually ramps up the switch current limit from about 100ma to the switchs maximum current limit in typical value of 150s, as shown in figure 8. this feature limits the inrush current during start-up and prevents the switch current from spik- ing when the en/uvlo pin crosses the uvlo threshold. a soft-start sequence is also initiated right after a v in overvoltage/undervoltage lockout, or thermal shutdown fault in order to prevent the switch current from suddenly jumping to its maximum current limit. applications information figure 7. lt3689 minimum v in to start and run vs load figure 8. internal soft-start 20s/div v out 2v/div v in = 12v v out = 5v f = 2mhz c in = 1f ceramic + 100f electrolytic i vin 0.2a/div i l 0.5a/div 3689 f08 load (ma) 1 7.0 v in (v) 7.5 10 100 1000 6.5 6.0 5.5 5.0 8.0 3589 f07a to start: en/uvlo tied to v in to run v out = 5v l = 8.2h f sw = 800khz t a = 25c to start: en/uvlo high threshold = 6.15v load (ma) 1 5.0 v in (v) 5.5 10 100 1000 4.5 4.0 3.5 3.0 6.0 3589 f07b to start: en/uvlo tied to v in to run v out = 3.3v l = 8.2h f sw = 800khz t a = 25c to start: en/uvlo high threshold = 4.85v
lt3689/lt3689-5 22 3689fa synchronization to select low ripple burst mode operation, tie the sync pin below 0.3v (this can be ground or a logic output). synchro- nizing the lt3689 oscillator to an external frequency can be done by connecting a square wave (with positive and negative pulse width >80ns) to the sync pin. the square wave amplitude should have valleys that are below 0.3v and peaks that are above 1v (up to 6v). the lt3689 will not enter burst mode operation at low output loads while synchronized to an external clock, but instead will skip pulses to maintain regulation. the lt3689 may be synchronized over a 350khz to 2.5mhz range. the r t resistor should be chosen to set the lt3689 switching frequency 20% below the lowest synchronization input. for example, if the synchronization signal will be 350khz and higher, the r t should be chosen for 280khz. to assure reliable and safe operation, the lt3689 will only synchronize when the output voltage is above 90% of its regulated voltage. it is therefore necessary to choose a large enough inductor value to supply the required output current at the frequency set by the r t resistor (see the inductor selection section). it is also important to note that the slope compensation is set by the r t value. when the sync frequency is much higher than the one set by r t , the slope compensation will be signi? cantly reduced, which may require a larger inductor value to prevent subharmonic oscillation. the minimum inductor value should be calculated using the rt programmed frequency to avoid subharmonic oscillation. shutdown and undervoltage lockout figure 9 shows how to add undervoltage lockout (uvlo) to the lt3689. typically, uvlo is used in situations where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where the problems might occur. an internal comparator will force the part into shutdown below the minimum v in of 3.4v. this feature can be used to prevent excessive discharge of battery-operated systems. if an adjustable uvlo threshold is required, the en/uvlo pin can be used. the threshold voltage of the en/uvlo pin comparator is 1.26v. current hysteresis is added above the en threshold. this can be used to set voltage hysteresis of the uvlo using the following: r3 = v h v l 4a 4k r4 = 1.26v v h 1.26v r3 4a applications information figure 9. undervoltage lockout 1.25v 4a r3 r4 c1 en/uvlo lt3689 v in ss v c 3689 f09 C +
lt3689/lt3689-5 23 3689fa example: switching should not start until the input is above 4.40v, and is to stop if the input falls below 4v. v h = 4.40v,v l = 4v r3 = 4.40v ? 4v 4a ? 4k = 95.3k r4 = 1.26v 4.40v ? 1.26v 95.3k ?4a = 43.2k (nearest 1% resistor) keep the connection from the resistor to the en/uvlo pin short and make sure the interplane or surface capaci- tance to switching nodes is minimized. if high resistor values are used, the en/uvlo pin should be bypassed with a 1nf capacitor to prevent coupling problems from the switch node. output voltage monitoring the lt3689 provides power supply monitoring for micro- processor-based systems. the features include power-on reset (por) and watchdog timing. a precise internal voltage reference and glitch immune precision por comparator circuit monitor the lt3689 output voltage. the switchers output voltage must be above 90% of programmed value for rst not to be as- serted (refer to the timing diagram). the lt3689 will assert rst during power-up, power-down and brownout conditions. once the output voltage rises above the rst threshold, the adjustable reset timer is started and rst is released after the reset timeout period. on power-down, once the output voltage drops below rst threshold, rst is held at a logic low. the reset timer is adjustable using external capacitors. the rst pin has a weak pull-up to the out pin. the por comparator is designed to be robust against fb pin noise, which could potentially false trigger the rst pin. the por comparator lowpass ? lters the ? rst stage of the comparator. this ? lter integrates the output of the compara- tor before asserting the rst . the bene? t of adding this ? lter is that any transients at the buck regulators output must be of suf? cient magnitude and duration before it triggers a logic change in the output (see the typical transient vs por comparator overdrive in the typical performance characteristics section). this prevents spurious resets caused by output voltage transients such as load steps or short brownout conditions without sacri? cing the dc reset threshold accuracy. watchdog the lt3689 includes an adjustable watchdog timer that monitors a ps activity. if a code execution error occurs in a p , the watchdog will detect this error and will set the wdo low. this signal can be used to interrupt a routine or to reset a microprocessor. the watchdog is operated either in timeout or window mode. in timeout mode, the microprocessor needs to toggle the wdi pin before the watchdog timer expires, to keep the wdo pin high. if no wdi pulse (either positive or negative) appears during the programmed timeout period, then the circuitry will pull wdo low. during normal opera- tion, the wdi input signals high to low, and low to high transition periods should be set lower than the watchdogs programmed time to keep wdo inactive. in window mode, the watchdog circuitry is triggered by negative edges on the wdi pin. the window mode restricts the wdi pins negative going pulses to appear inside a programmed time window (see the timing diagram) to prevent wdo from going low. if more than two pulses are registered in the watchdog lower boundary period, the wdo is forced to go low. the wdi edges are ignored while the c wdt capacitor charges from 0v to 200mv right after a low to high transition on the wdo or rst pin. the wdo also goes low if no negative edge is supplied to the wdi pin in the watchdog upper boundary period. during a code execution error, the microprocessor will output wdi pulses that would be either too fast or too slow. this condition will assert wdo and force the microprocessor to reset the program. in window mode, the wdi signal frequency is bounded by an upper and lower limit for normal operation. the wdi input frequency period should be higher than the t wdl period, and lower than the t wdu period, to keep wdo high under normal conditions. the window modes t wdl and t wdu times have a ? xed ratio of 31 between them. these times can be increased or decreased by adjusting an external capacitor on the c wdt pin. applications information
lt3689/lt3689-5 24 3689fa in both watchdog modes, when wdo is asserted, the reset timer is enabled. any wdi pulses that appear while the reset timer is running are ignored. when the reset timer expires, the wdo is allowed to go high again. therefore, if no input is applied to the wdi pin, then the watchdog circuitry produces a train of pulses on the wdo pin. the high time of this pulse train is equal to the timeout period, and low time is equal to the reset period. also, wdo and rst cannot be logic low simultaneously. if wdo is low and rst goes low, then wdo will go high. the wde pin allows the user to turn on and off the watchdog function. do not leave this pin open. tie it high or low to turn watchdog off or on, respectively. the w /t pin enables/disables the window/timeout mode. leaving this pin open is ? ne and will put the watchdog in window mode. it has a weak pull-down to ground. the wdi pin has an internal 2a weak pull-up that keeps the wdi pin high. if watchdog is disabled, leaving this pin open is acceptable. selecting the reset timing capacitors the reset timeout period is adjustable in order to accom- modate a variety of microprocessor applications. the reset timeout period, (t rst ), is adjusted by connecting a capacitor, c por , between the c por pin and ground. the value of this capacitor is determined by: c por = t rst ? 432 pf ms this equation is accurate for reset timeout periods of 5ms, or greater. to program faster timeout periods, see the reset timeout period vs capacitance graph in the typical performance characteristics section. leaving the c por pin unconnected will generate a minimum reset applications information figure 10. reset timer waveforms figure 11. window watchdog waveforms ( w /t = low) figure 12. timeout watchdog waveforms ( w /t = high) 50ms/div v out 2v/div c por 1v/div rst 2v/div 3689 f10 t rst = 165ms c por = 71nf 5ms/div c wdt 1v/div c por 1v/div wdi 5v/div wdo 2v/div 3689 f11 c wdt = 10nf, t wdl = 5.8ms 100ms/div c wdt 1v/div c por 1v/div wdi 5v/div wdo 2v/div 3689 f12 t rst = 165ms, c por = 71nf t wdu = 180ms, c wdt = 10nf
lt3689/lt3689-5 25 3689fa timeout of approximately 25s. maximum reset timeout is limited by the largest available low leakage capacitor. the accuracy of the timeout period will be affected by capacitor leakage (the nominal charging current is 2a) and capacitor tolerance. a low leakage ceramic capacitor is recommended. selecting the watchdog timing capacitor the watchdog timeout period is adjustable and can be optimized for software execution. the watchdog upper boundary timeout period, t wdu is adjusted by connect- ing a capacitor, c wdt , between the c wdt pin and ground. given a speci? ed watchdog timeout period, the capacitor is determined by: c wdt = t wdu ?55 pf ms this equation is accurate for upper boundary periods of 20ms, or greater. the watchdog lower boundary period (t wdl ) has a ? xed relationship to t wdu for a given capacitor. the t wdl period is related to t wdu by the following: tt wdl wdu = 1 31 ? in addition, the following equation can be used to calculate the watchdog lower boundary period for a given c wdt capacitor value. ct nf ms wdt wdl = ? . 17 these lower boundary period equations are accurate for a t wdl of 3ms, or greater. to program faster t wdu and t wdl periods, see the watchdog upper and lower boundary periods vs capacitance graphs in the typical performance characteristics section. leaving the c wdt pin unconnected will generate a minimum watchdog timeout of approximately 200s. maximum timeout is limited by the largest available low leakage capacitor. the accuracy of the timeout period will be af- fected by capacitor leakage (the nominal charging current is 2a) and capacitor tolerance. a low leakage ceramic capacitor is recommended. shorted and reversed input protection if an inductor is chosen to prevent excessive saturation, the lt3689 will tolerate a shorted output. when operat- ing in short-circuit condition, the lt3689 will reduce its frequency until the valley current is at a typical value of 1.2a (see figure 13). there is another situation to consider in systems where the output will be held high when the input to the lt3689 is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ored with applications information figure 13. the lt3689 reduces its frequency to below 100khz to protect against shorted output with 36v input figure 14. diode d4 prevents a shorted input from discharging a backup battery tied to the output; it also protects the circuit from a reversed input. the lt3689 runs only when the input is present v in 3689 f14 en/uvlo bst sw lt3689 out gnd da fb v in v out + 10s/div v sw 20v/div i l 0.5a/div 3689 f13
lt3689/lt3689-5 26 3689fa the lt3689s output. if the v in pin is allowed to ? oat and the en/uvlo pin is held high (either by a logic signal or because it is tied to v in ), then the lt3689s internal circuitry will pull its quiescent current through its sw pin. this is ? ne if the system can tolerate a few ma in this state. if the en/uvlo pin is grounded, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt3689 can pull large currents from the output through the sw pin and the v in pin. figure 14 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 15 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents ? ow in the lt3689s v in and sw pins, the catch diode (d1) and the input capacitor (c1). the loop formed by these components should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board. place a local, unbroken ground plane below these components. the sw and bst nodes should be as small applications information figure 15. example layout for qfn package. a good pcb layout ensures proper low emi operation
lt3689/lt3689-5 27 3689fa as possible. finally, keep the fb node small so that the ground traces will shield them from the sw and boost nodes. the exposed pad on the bottom of the package must be soldered to ground so that the pad acts as a heat sink. to keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the lt3689 to additional ground planes within the circuit board and on the bottom side. high temperature considerations the pcb must provide heat sinking to keep the lt3689 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these layers will spread the heat dissipated by the lt3689. placing additional vias can reduce thermal resistance further. because of the large output current capability of the lt3689, it is possible to dissipate enough heat to raise the junction temperature beyond the absolute maximum of 125c (150c for h-grade). when operating at high ambient temperatures, the maximum load current should be derated as the ambient temperature approaches 125c (150c for h-grade). a board measuring 5cm 7.5cm with a top layer layout similar to figure 15 was evaluated in still air at 3.3v out , 700khz switching frequency. at 700ma load, the temperature reached approximately 12c above ambient for input voltages equal to 12v and 24v. power dissipation within the lt3689 can be estimated by calculat- ing the total power loss from an ef? ciency measurement and subtracting the catch diode loss. the die temperature is calculated by multiplying the lt3689 power dissipation by the thermal resistance from junction-to-ambient. other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note 318 shows how to generate a bipolar output supply using a buck regulator. applications information typical applications sw da fb rt sync f sw = 1mhz wdi rst wdo v in en/uvlo v in 6.3v to 36v transient to 60v 5v 700ma r2 102k l1 12h c2 0.1f d1 c3 10f r1 536k gnd r t 12.7k lt3689 3689 ta02 bst out c por c wdt c1 1f i/o i/o reset p w /t window timeout wde watchdog_defeat c6 10nf t wdu = 182ms l1: cdr125np-12mc d1: mbrm140 c1, c2, c3: x7r or x5r c4 5.6pf c5 68nf t rst = 157ms 5v step-down converter
lt3689/lt3689-5 28 3689fa typical applications sw da fb rt sync f sw = 700khz wdi rst wdo v in en/uvlo v in 4.5v to 36v transient to 60v 3.3v 700ma r2 100k l1 12h c2 0.1f d1 c3 22f r1 316k gnd r t 20.5k lt3689 3689 ta03 bst out c por c wdt c1 2.2f i/o i/o reset p w /t window timeout wde watchdog_defeat c6 10nf t wdu = 182ms l1: cdr125np-12mc d1: mbrm140 c1, c2, c3: x7r or x5r c4 10pf c5 68nf t rst = 157ms 3.3v step-down converter sw da fb rt sync f sw = 2mhz wdi rst wdo v in en/uvlo v in 6.3v to 18v transient to 60v 5v 700ma l1 10h c2 0.1f d1 c3 4.7f gnd r t 4.02k lt3689-5 3689 ta04 bst out c por c wdt c1 1f i/o i/o reset p w /t window timeout wde watchdog_defeat c6 10nf t wdu = 182ms c1, c2, c3: x7r or x5r d1: mbrm140 c4 2.7pf c5 68nf t rst = 157ms 5v, 2mhz step-down converter
lt3689/lt3689-5 29 3689fa package description msop (mse16) 0608 rev a 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 12345678 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev a) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref
lt3689/lt3689-5 30 3689fa package description 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom viewexposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 s 45 o chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 p 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691)
lt3689/lt3689-5 31 3689fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 04/10 added lt3689-5 fixed output voltage option 1C32
lt3689/lt3689-5 32 3689fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0410 rev a ? printed in usa related parts typical application part number description comments lt1766 60v, 1.2a (i out ), 200khz, high ef? ciency step-down dc/dc converter v in : 5.5v to 60v, v out(min) = 1.20v, i q = 2.5ma, i sd = 25a, tssop-16 and tssop-16e packages lt1936 36v, 1.4a (i out ), 500khz high ef? ciency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 1.2v, i q = 1.9ma, i sd <1a, ms8e package lt1976/lt1977 60v, 1.2a (i out ), 200khz/500khz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out(min) = 1.20v, i q = 100a, i sd <1a, tssop-16e package lt3434/lt3435 60v, 2.4a (i out ), 200khz/500khz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out(min) = 1.20v, i q = 100ma, i sd <1a, tssop-16e package lt3437 60v, 400ma (i out ), micropower step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out(min) = 1.25v, i q = 100a, i sd <1a, 3mm 3mm dfn-10 and tssop-16e packages lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.6v to 38v, v out(min) = 0.78v, i q = 70a, i sd <1a, 3mm 3mm dfn-10 and msop-10e packages lt3481 34v with transient protection to 36v, 2a (i out ), 2.8mhz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.6v to 34v, v out(min) = 1.26v, i q = 50ma, i sd <1a, 3mm 3mm dfn-10 and msop-10e packages lt3493 36v, 1.4a (i out ), 750khz high ef? ciency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 1.9ma, i sd <1a, 2mm 3mm dfn-6 package lt3500 36v, 40v max , 2a, 2.5mhz high ef? ciency step-down dc/dc converter and ldo controller v in : 3.6v to 36v, v out(min) = 0.8v, i q = 2.5ma, i sd <10a, 3mm 3mm dfn-10 package lt3505 36v with transient protection to 40v, 1.4a (i out ), 3mhz, high ef? ciency step-down dc/dc converter v in : 3.6v to 34v, v out(min) = 0.78v, i q = 2ma, i sd = 2a, 3mm 3mm dfn-8 and msop-8e packages lt3507 36v 2.5mhz, triple (2.4a + 1.5a + 1.5a (i out )) with ldo controller high ef? ciency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 2.5ma, i sd = 10a, tssop-16 and tssop-16e packages lt3508 36v with transient protection to 40v, dual 1.4a (i out ), 3mhz, high ef? ciency step-down dc/dc converter v in : 3.7v to 37v, v out(min) = 0.8v, i q = 4.6ma, i sd = 1a, 4mm 4mm qfn-24 and tssop-16e packages lt3682 36v, 60v max , 1a, 2.2mhz high ef? ciency micropower step- down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 75ma, i sd <1a, 3mm 3mm dfn-12 package lt3684 34v with transient protection to 36v, 2a (i out ), 2.8mhz, high ef? ciency step-down dc/dc converter v in : 3.6v to 34v, v out(min) = 1.26v, i q = 850a, i sd <1a, 3mm 3mm dfn-10 and msop-10e packages lt3685 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high ef? ciency step-down dc/dc converter v in : 3.6v to 38v, v out(min) = 0.78v, i q = 70a, i sd <1a, 3mm 3mm dfn-10 and msop-10e packages sw da fb rt sync f sw = 900khz wdi rst wdo v in en/uvlo v in 3.6v to 16v transient to 27v 1.8v 700ma r2 102k l1 4.7h c2 0.1f d1 c3 47f r1 127k gnd r t 14.7k lt3689 3689 ta05 bst out c por c wdt c1 1f i/o reset p w /t window timeout wde watchdog_defeat c6 10nf t wdu = 182ms l1: we-pd2: 7447745047 d1: mbrm140 c1, c2, c3: x7r or x5r c4 15pf c5 68nf t rst = 157ms 1.8v step-down converter with system reset generated by watchdog timing or output voltage failure

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